Projects (national and international)
| Project name | From | To | Grant Agreement |
|---|---|---|---|
| 1.7 Tecnologie per la penetrazione efficiente del vettore elettrico negli usi finali | 2022 | 2024 | — |
| PNRR CN4 – Mobilità Sostenibile – Spoke 13 – Trazione elettrica e batterie | 2022 | 2024 | I53C22000720001 |
| European Processor Initiative (EPI) – SGA2 (https://www.european-processor-initiative.eu/) | 2022 | 2024 | 101036168 |
| European Processor Initiative (EPI) – SGA1 (https://cordis.europa.eu/project/id/826647) | 2018 | 2021 | 826646 |
Research Activity
- January 2023 – Present day
- Development of embedded security modules with innovative cybersecurity functionalities for the protection of Battery Management Systems (BMSs) for lithium-ion batteries in sustainable mobility applications.
- Development of embedded security modules with innovative cybersecurity functionalities for the protection of Battery Management Systems (BMSs) for lithium-ion batteries in sustainable mobility applications.
- January 2022 – Present day
- Development and synthesis on a 7 nm standard-cell technology of security modules with advanced and innovative functionalities for the processor EPI Rhea2; in particular, a co-processor for post-quantum public-key cryptography, a co-processor for holomorphic encryption, a high-speed memory encryption module, and an improved and enhanced version of the cryptographic co-processor Crypto-Tile that was integrated into the processor EPI Rhea. Development of the corresponding cycle-accurate functional models. Activity performed in collaboration with several partners of the EPI consortium.
- Development and validation on an FPGA device KU115 of modules of the receiving back-end chain for satellite communications compliant with the standard CCSDS 131.2-B-1 and supporting high symbol rates (> 1 Gbaud); in particular, innovative and parallel-architecture-based modules for the frames synchronization, the CC2 de-puncturing, and the hardware/software interfacing. Activity performed in collaboration with IngeniArs S.r.l.
- Development of cycle-accurate functional equivalent models for the cryptographic co-processor Crypto-Tile that was developed for the security sub-system of the processor EPI Rhea. Activity performed in collaboration with several partners of the EPI consortium.
- October 2019 – January 2020
- Development of a module for the iterative decoding of turbo-codes and relying on the BCJR algorithm for telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Activity performed in collaboration with IngeniArs S.r.l.
- Development of a module for the iterative decoding of turbo-codes and relying on the BCJR algorithm for telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Activity performed in collaboration with IngeniArs S.r.l.
- September 2019 – December 2019
- Development of a bit-true model for the performance analysis, and the estimation of the hardware complexity and accuracy in terms of BER (Bit Error Rate) and CER (Codeword Error Rate) for a module aimed at the iterative decoding of turbo-codes and relying on the BCJR algorithm for telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Activity performed in collaboration with IngeniArs S.r.l.
- Development of a bit-true model for the performance analysis, and the estimation of the hardware complexity and accuracy in terms of BER (Bit Error Rate) and CER (Codeword Error Rate) for a module aimed at the iterative decoding of turbo-codes and relying on the BCJR algorithm for telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Activity performed in collaboration with IngeniArs S.r.l.
- January 2019 – March 2019
- Development of an encryption module with self-synchronization mechanisms in case of data packet loss for the security of audio communications between the microphone and the receiving base station. Activity performed in collaboration with IngeniArs S.r.l. and Wisycom.
- Development of an encryption module with self-synchronization mechanisms in case of data packet loss for the security of audio communications between the microphone and the receiving base station. Activity performed in collaboration with IngeniArs S.r.l. and Wisycom.
- October 2018 – December 2021
- Development, synthesis on a 7 nm standard-cell technology, and validation on an FPGA demoboard of an advanced cryptographic co-processor (named Crypto-Tile) for the support of the secure boot routine and the configuration of the security sub-system of the general-purpose processor Rhea from the project European Processor Initiative (EPI). Activity performed in collaboration with several partners of the EPI consortium.
- Development, synthesis on a 7 nm standard-cell technology, and validation on an FPGA demoboard of an advanced cryptographic co-processor (named Crypto-Tile) for the support of the secure boot routine and the configuration of the security sub-system of the general-purpose processor Rhea from the project European Processor Initiative (EPI). Activity performed in collaboration with several partners of the EPI consortium.
- April 2017 – September 2018
- Development of a real-time hardware digital firewall for automotive CAN networks equipped with mechanisms for preventing Denial-of-Service (DoS) attacks and supporting adaptive filtering rules based on message characteristics such as content, protocol identifiers, and timing. Activity performed in collaboration with Marelli Europe SpA.
- Development of a cybersecurity embedded system compliant with the standard IEEE 1609.2 for the protection of wireless automotive networks aimed at V2V (Vehicle-to-Vehicle) and V2X (Vehicle-to-Everything) communications. Activity performed in collaboration with Intel.
- May 2015 – June 2016
- Development of an environment for the analysis of the vulnerabilities and the validation of the corresponding countermeasures against Side-Channel attacks of the Power Analysis type. Activity performed in collaboration with Renesas Electronics Europe GmbH.
- Development of a half-duplex hardware accelerator for the security protection of the Automotive Ethernet networks through the MACsec algorithm and compliant with the standards d IEEE 802.1AE, IEEE 802.1AEbn e IEEE 802.1AEbw. Activity performed in collaboration with Renesas Electronics Europe GmbH.
- Development of a full-duplex hardware accelerator for the security protection of the Automotive Ethernet networks through the MACsec algorithm and compliant with the standards d IEEE 802.1AE, IEEE 802.1AEbn e IEEE 802.1AEbw. Activity performed in collaboration with Renesas Electronics Europe GmbH.
Technology Transfer
- Intellectual Property of a hardware acceleration module for the MACsec algorithm in full-duplex mode and compliant with the standards IEEE 802.1AE, IEEE 802.1AEbn, and IEEE 802.1AEbw for the security protection of data on Automotive Ethernet networks. Transferred to Renesas Electronics Europe GmbH with TRL 3 and implemented as a module described using the hardware description language (HDL) Verilog at Register-Transfer-Level (RTL) for the integration into the automotive processors of Renesas.
- Intellectual Property of a hardware acceleration module for the MACsec algorithm in half-duplex mode and compliant with the standards IEEE 802.1AE, IEEE 802.1AEbn, and IEEE 802.1AEbw for the security protection of data on Automotive Ethernet networks. Transferred to Renesas Electronics Europe GmbH with TRL 3 and implemented as a module described using the hardware description language (HDL) Verilog at Register-Transfer-Level (RTL) for the integration into the automotive processors of Renesas.
- Intellectual Property (named DDD, Digital Data Diode) of an innovative real-time hardware digital firewall for automotive CAN networks equipped with mechanisms for adaptive filtering rules and minimization of the bus occupation overhead. Transferred to Marelli Europe SpA with TRL 5 and implemented as a module described using the hardware description language (HDL) Verilog at Register-Transfer-Level (RTL) and validated the Bologna site of Marelli Europe SpA through an FPGA prototype that was applied to Giulietta car from Alfa Romeo. The achieved innovation level brought to the three patent applications IT201800021550A1, CN111385286B, and JP2020109953A (that are reported in the corresponding section).
- Intellectual Property (named Crypto-Tile) of a cryptographic co-processor for advanced and long-term security services in terms of both classical security and post-quantum security. Transferred to the consortium of the project European Processor Initiative (EPI) with TRL 4 e and implemented as a module described using the hardware description language (HDL) SystemVerilog at Register-Transfer-Level (RTL) for the manufacturing of the Rhea chip on a 7 nm standard-cell technology.
- Firmware for programming an FPGA board VCU128 to implement a System-on-Chip (SoC) consisting of a 64-bit RISC-V CVA6 processor, an AXI4 buse, a DDR memory, and the IP Crypto-Tile. Transferred to the consortium of the project European Processor Initiative (EPI) with TRL 4 for the development of bare-metal software drivers and Linux kernel drivers to support the hardware acceleration of the security functions of the security sub-system of the first family of EPI processors (Rhea).
- Intellectual Property of a hardware encryption module for the protection of audio communications between the microphone and the receiving base station and equipped with self-synchronization mechanisms in case of packet data loss. Transferred to IngeniArs S.r.l. with TRL 3 and implemented as a module described using the hardware description language (HDL) VHDL at Register-Transfer-Level (RTL) for the integration into the receiver developed by IngeniArs S.r.l. for Wisycom.
- Intellectual Property of a bit-true multi-thread model accelerated in C for the iterative decoding of turbo-codes in high data-rate telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Transferred to IngeniArs S.r.l. with TRL 3 and implemented in MATLAB for the analysis and the estimation of the accuracy and the hardware complexity of corresponding decoding modules implemented in HDL and according to several configuration parameters.
- Intellectual Property of a hardware module for the iterative decoding of turbo-codes in high data-rate telemetry applications in space communications compliant with the standard CCSDS 131.2-B-1. Transferred to IngeniArs S.r.l. with TRL 3 and implemented as a module described using the hardware description language (HDL) VHDL at Register-Transfer-Level (RTL) for the integration into the satellite receivers developed by IngeniArs S.r.l, and validated on an FPGA device KU115.
- Intellectual Property of a hardware module for the frame synchronization and the phase correction inside satellite receivers compliant with the standard CCSDS 131.2-B-1 and supporting symbol rates greater than or equal to 1 Gbaud, and corresponding testing environment. Transferred to IngeniArs S.r.l. with TRL 4 and implemented as a module described using the hardware description language (HDL) VHDL at Register-Transfer-Level (RTL) for the integration into the corresponding satellite receiver developed by IngeniArs S.r.l, and validated on an FPGA device KU115.
- Intellectual Property of a hardware module for the CC2 de-puncturing function and the Clock Domain Crossing (CDC) mechanisms inside satellite receivers compliant with the standard CCSDS 131.2-B-1 and supporting symbol rates greater than or equal to 1 Gbaud, and corresponding testing environment. Transferred to IngeniArs S.r.l. with TRL 4 and implemented as a module described using the hardware description language (HDL) VHDL at Register-Transfer-Level (RTL) for the integration into the corresponding satellite receiver developed by IngeniArs S.r.l, and validated on an FPGA device KU115.
- Intellectual Property of a hardware module corresponding to the back-end chain of a satellite receiver compliant with the standard CCSDS 131.2-B-1 and supporting symbol rates greater than or equal to 1 Gbaud, and consisting of the other IPs already transferred to IngeniArs S.r.l., other IPs developed by IngeniArs S.r.l., and an additional ad-hoc IP for the hardware/software interfacing. Transferred to IngeniArs S.r.l. with TRL 4 and implemented as a module described using the hardware description language (HDL) VHDL at Register-Transfer-Level (RTL) for the development of the satellite receiver by IngeniArs S.r.l, and validated on an FPGA device KU115.