Teaching

In this section, it is possible to find the relevant teaching material for each course divided by academic year or the link to the corresponding team on Microsoft Teams, where the teaching material has been and is progressively uploaded. There is also ancillary and additional teaching material related to general knowledge, cross-curricular knowledge, and useful insights for students in engineering areas.

Courses teaching material

Course Laboratorio di Elettronica (101II), 6 ECTS. Bachelor’s Degree in Electronic Engineering from the University of Pisa.
Course Electronics Systems (938II), 6 ECTS. Master’s Degree in Cybersecurity from the University of Pisa.
Course Hardware and Embedded Security (930II), 9 ECTS. Master’s Degree in Cybersecurity from the University of Pisa.
Course Principles of Cybersecurity and the Role of Hardware in Security, 4 ECTS (16 hours).
  • Educational offer for PhD Program in Information Engineering, University of Pisa, Academic Year 2023/2024: link to the team.

Additional materials on general skills, soft skills, and insights

  • Quick guide for technical and scientific documents (report, user guide, thesis, paper, …)
    • Dedicated article at this link.
  • Notes and recalls on the frequency response of electronic systems
    • Link (coming soon).
  • Quick and practical guide to synchronization techniques in multi-clock digital projects
    • Cummings, C. (2008). Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog. Sunburst Design Inc.
    • Online resource available here.
  • Survey of major clock gating techniques and their characteristics
    • Kathuria, J., Ayoubkhan, M., & Noor, A. (2011). A review of clock gating techniques. MIT International Journal of Electronics and Communication Engineering, 1(2), 106-114.
    • Online resource available here.
  • Quick and practical guide to reset techniques in digital designs and implementation of related distribution networks
    • Cummings, C., Mills, D., & Golson, S. (2003). Asynchronous & Synchronous Reset Design Techniques – Part Deux. Revision 1.3. In Proceedings of Conference Synopsys User Guide (SNUG) 2003.
    • Cummings, C., & Mills, D. (2002). Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?. Revision 1.1. In Proceedings of Conference Synopsys User Guide (SNUG) 2002.
    • Online resources available: rev 1.3 (2003), e rev 1.1 (2002).
  • Guide to the UVM methodology in SystemVerilog
    • Accellera System Initiative. (2014). Universal Verification Methodology (UVM) 1.2 Class Reference.
    • Online resource available here.
  • Quick guide to the design and the verification in SystemVerilog
    • Tutorial on the website ASIC-World (link).